Semiconductor devices such as ball grid array (e.g., BGA) packaged ICs are subject to a testing process prior to their final completion or incorporation into electronic apparatus. The testing process includes but is not limited to, testing of singulated or electrically isolated devices either bare die, packaged IC (temporary or permanent), or variants in between. Commonly, electrical testing is accomplished using automatic test equipment (ATE) configured for electrically stimulating semiconductor devices and then examining their output responses for proper functioning. In general, contactor pins associated with the ATE are placed in physical and electrical contact with metalized contact surfaces of a device under test (DUT). These surfaces may include test pads, bond pads, solder balls, leads and/or other conductive media. The functioning of DUTs may be tested by invoking stimuli on various inputs and then measuring responses sensed on outputs at the metalized contact surfaces.
Generally, a tester load board formed from a printed circuit board (PCB) or other media provides interface between an ATE and DUTs. The tester load board conventionally includes one or more contactor assembly, sometimes referred to as “test socket(s)” into which DUT(s) is (are) inserted. During automated testing, a DUT, such as a thin-shrink small outline package (TSSOP) for example, is thrust into the socket by a handler and held into position for the duration of testing. While held in the socket, contact surfaces on the DUT, such as leads, in the case of a TSSOP, make contact with the contactor pins. After insertion into the contactor, the DUT is electrically connected to the ATE through the tester load board, its sub-assemblies, and other interfacing apparatus. For the purpose of illustration, a DUT is brought into contact with pogo pins carried by a contactor body and coupled by a tester load board to an ATE. The ATE is generally supplied with software that includes the stimulus and response recipe required to test the proper functioning of a specific DUT.
Typically, a test “lot” includes numerous devices tested serially or in parallel which are subjected to the same testing process. A device handler thrusts DUTs into sockets where they are held in position, tested, removed, and then either rejected or accepted based on the results obtained by the ATE.
This type of testing presents technical challenges in verifying the proper functioning of DUTs while avoiding false readings which result in the erroneous rejection of operable DUTs. One of the challenges encountered in this type of testing is ensuring adequate electrical contact between the contactor's pins and the contact surfaces of the DUT. Poor electrical contact, caused by for example the presents of contaminates (e.g., debris), can result in erroneous test readings. These readings can be indicative of IC failure modes to include continuity, functional, parametric or others common to semiconductor testing. When erroneous readings are encountered, these can lead to the false rejection of otherwise good DUTs resulting in needless yield loss. However, some yield recovery may be possible through retesting. By either accepting the erroneous yield loss or by retesting to achieve recovery, production costs are elevated.